Fujitsu FR81S User Manual
CHAPTER 21: 32-BIT FREE-RUN TIMER
7. Q&A
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
7.5. About Interrupt Related Registers?
This section shows interrupt related registers.
Free-run timer interrupt vector and free-run timer interrupt level settings
The relationship between free-run timer numbers, interrupt levels and interrupt vectors is as shown in "4.
Table of Interrupt Vector" in "APPENDIX".
For details of the interrupt levels and interrupt vectors, see "CHAPTER: INTERRUPT CONTROL
(INTERRUPT CONTROLLER)".
Number
Interrupt vector (default)
Interrupt level setting bit (ICR[4:0])
Free-run timer 3
#50
Address: 0F_FF34
H
Interrupt level register (ICR34)
Address: 0_0462
H
Free-run timer 4
#51
Address: 0F_FF30
H
Interrupt level register (ICR35)
Address: 0_0463
H
Free-run timer 5
#50
Address: 0F_FF34
H
Interrupt level register (ICR34)
Address: 0_0462
H
Refer “Appendix C. List of Interrupt Vector” for ch.4 and ch.5.
Since interrupt request flags (TCCSn.ICLR [n=3 to 5]) will not be cleared automatically, clear the flags using
software before returning from interrupt processing. (Write "0" to the ICLR bit)
MB91520 Series
MN705-00010-1v0-E
834