Fujitsu FR81S User Manual
CHAPTER 22: 32-BIT OUTPUT COMPARE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
4.1. Output Control Register (Upper Bit) : OCSH
The bit configuration of the output control register (Upper bit) is shown below.
This register is to control operations of the output compare.
x: Channel number 6, 8, and 10.
y: Channel number 7, 9, and 11.
OCSHxy (Output compare xy): Address Base_addr+0A
H
(Access: Byte,
Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
Reserved Reserved CMOD Reserved Reserved OTDy
OTDx
Initial value
X
1
1
0
0
0
0
0
Attribute RX,WX
R1,W1
R1,W1
R/W
R/W0
R/W0
R,W
R,W
[bit15] : Undefined
The read value is undefined.
Writing has no effect on operation.
[bit14, bit13] : Reserved
The read value is "1".
The written value is "1".
[bit12] CMOD : Output level switch mode
CMOD
Operating mode
0
Independent operation (OCU6 to OCU11 pins output level invert operation is independent.)
OCU6, 8, 10 pins: When the free-run timer value corresponds to the compare register 6, 8, 10
(OCCP6, 8, 10) value, the output is inverted.
OCU7, 9, 11 pins: When the free-run timer value corresponds to the compare register 7, 9, 11
(OCCP7, 9, 11) value, the output is inverted.
The comparison target free-run timer is selected by FRS8 register.
1
Coordinated operation
OCU6, 8, 10 pins: When the free-run timer value corresponds to the compare register 6, 8, 10
(OCCP6, 8, 10), the output is inverted.
OCU7, 9, 11 pins: When the free-run timer value corresponds to either the compare register (6 or
7), (8 or 9), (10 or 11), the output is inverted.
The comparison target free-run timer is selected by FRS8 register.
⋅
When the compare register 6 and 7 have the same value, the operation is the same one as when only one
compare register is used. Same as the compare register 8 to 11.
[bit11, bit10] : Reserved
The read value is "0".
The written value is "0".
MB91520 Series
MN705-00010-1v0-E
845