Fujitsu FR81S User Manual
CHAPTER 22: 32-BIT OUTPUT COMPARE
9. Notes
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
9. Notes
This section explains the notes of the 32-bit output compare.
About the compare stop interval during compare operation
For one count right after the writing of a compare value to the compare register, there is no compare operation
as shown below.
⋅
For the setting of CMOD= "1" and OCCP6 = OCCP7, when compare match occurs, the port inverts only
once. (Similar in ch.8 to ch.11)
⋅
When the output level of compare output pins (OCU6 to OCU11) is specified, first stop the compare
operation, and then specify it.
⋅
Because the 32-bit output compare is synchronized with the free-run timer, when the free-run timer is
stopped, the compare operation also is stopped.
⋅
When the compare mode bit is set to CMOD = "1" also, the interrupt operation occurs for each OCU6
and OCU7 independently. (Similar in ch.8 to ch.11)
⋅
When the free-run timer is used as the compare data of the output compare, the setting of
"0000
B
"(1/F
PCLK
) is disabled for the free-run timer clock frequency TCCSL.CLK[3:0].
⋅
About read-modify-write
When the interrupt request flag bits (IOP6 to IOP11) are read with read-modify-write instruction, "1"
is read.
⋅
About interrupt
Please clear "0" to the compare match interrupt request flag (IOPx) to return from the interrupt
processing when "1" is set to compare match interrupt request flag (IOPx) of the compare control
register, and the compare match interrupt request is permitted next (IOEx="1").
N
-
2
N
-
1
N
N+1
N+2
N+3
X
N
Writing to compare register
Compare
timing
Compare stop interval
In this case, a match signal is not generated.
N
-
2
N
-
1
N
N+1
N+2
N+3
X
N
Count value of free-run timer
Compare register value
MB91520 Series
MN705-00010-1v0-E
876