Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4
2. Features
This section explains features of the 32-bit input capture.
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Format :
Edge detection circuit + 32-bit buffer (capture register)
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Number of units : 6
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Edge detection : Rising/falling/both edges
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Interrupt :
Edge detection interrupt
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Capture value :
Timer count value (00000000
H-
to FFFFFFFF
H
)
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Timer :
Use free-run timer 3 to 5.
Please refer to the chapter of "32-BIT FREE-RUN TIMER" for the selection method.
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Precision:
Peripheral clocks (PCLK)/1,/2, /4, /8, /16, /32, /64, /128, /256)
(count clock of the free-run timer)
Count value
of free-run
timer
Capture signal
Buffer value
1FFFFFFF
H
1FFFFFFF
H
t
Cycle and pulse width measurement function
The cycle and the pulse width can be measured by the following settings.
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When setting of rising edge detection : Cycle from rising edge to rising edge
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When setting of falling edge detection : Cycle from falling edge to falling edge
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When setting of both edge detection
: Cycle from rising edge to rising edge,
Cycle from falling edge to falling edge,
Pulse width from rising edge to falling edge,
Pulse width from falling edge to rising edge
MB91520 Series
MN705-00010-1v0-E
879