Fujitsu FR81S User Manual
CHAPTER 24: 16-BIT FREE-RUN TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.1.2.
Timer Synchronous Activation Enable Register :
TCGSE
The timer synchronous activation enable register (TCGSE) allows you to set the free-run timer that enables
the simultaneously activation/clear.
TCGSE: Address 1203
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
FRT2
FRT1
FRT0
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
[bit7 to bit3] Reserved
Always write 0 to these bits.
[bit2 to bit0] FRT2 to FRT0: Simultaneous activation/clear setting bits
FRT2 to FRT0
Function
0
Do not allow simultaneous activation/clear
1
Allow simultaneous activation/clear
⋅
These bits allow you to set the free-run timer that enables the simultaneous activation/clear.
⋅
When these bits are set to "0":
The free-run timer will not be activated nor cleared when configuring the timer synchronous activation
register (TCGS).
⋅
When these bits are set to "1":
The free-run timer will be activated or cleared when configuring the timer synchronous activation
register (TCGS).
MB91520 Series
MN705-00010-1v0-E
918