Fujitsu FR81S User Manual
CHAPTER 24: 16-BIT FREE-RUN TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
[bit11] MODE2 : Interrupt mask mode bit 2
MODE2
MODE*
Function
0
0
Value set for MSI5 to MSI3 will be invalid
0
1
Value set for MSI5 to MSI3 will be invalid
1
0
Setting disabled (operation is not guaranteed)
1
1
Value set for MSI5 to MSI3 will be valid
⋅
In the up/down count mode (MODE: bit21 of the timer state control register (TCCS) is 1) of the 16-bit
free-run timer, this bit will be used to mask the 0 detection interrupt and compare clear interrupt
independently.
⋅
During the MODE:bit21="1" of the timer state control register (TCCS) and if this bit is set to 1, the value
configured at MSI5 to MSI3: bit10 to bit8 of this register becomes valid and the compare clear interrupt is
masked for the number of times specified. For the mask count of 0 detection interrupt, the value configured
at MSI2 to MSI0: bit28 to bit26 of the timer state control register (TCCS) becomes valid.
Note:
During MODE:bit21="0" of the timer state control register (TCCS) and if this bit is set to "1", the operation
is not guaranteed.
[bit10 to bit8] MSI5 to MSI3 : Compare clear interrupt mask selection bits
MSI5
MSI4
MSI3
Function
0
0
0
An interrupt occurs when there is a match for the first time
0
0
1
An interrupt occurs when there is a match for the second time
0
1
0
An interrupt occurs when there is a match for the third time
0
1
1
An interrupt occurs when there is a match for the fourth time
1
0
0
An interrupt occurs when there is a match for the fifth time
1
0
1
An interrupt occurs when there is a match for the sixth time
1
1
0
An interrupt occurs when there is a match for the seventh time
1
1
1
An interrupt occurs when there is a match for the eighth time
⋅
These bits, which are used to configure the mask count of compare clear interrupt, are valid only when
MODE: bit21 of the timer state control register (TCCS) as well as MODE2: bit11 of this register are 1.
Value that can be configured for the mask count of 0 detection interrupt is MSI2 to MSI0: bit28 to bit26 of
the timer state control register (TCCS).
⋅
When these bits are set to "000
B
", the compare clear interrupt factor will not be masked.
MB91520 Series
MN705-00010-1v0-E
929