Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
4.2.1.
Serial Control Register: SCR
The serial control register (SCR) allows you to disable/enable transmission and reception, disable/enable
transmission/reception interrupts, disable/enable transmission bus idle interrupts, and reset UART.
SCRn(n=0 to 11): Address Base addr + 00
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
bit
UPCL Reserved Reserved
RIE
TIE
TBIE
RXE
TXE
0
-
-
0
0
0
0
0
Initial value
R0,W RX,WX RX,WX
R/W
R/W
R/W
R/W
R/W
Attribute
Bit name
Function
bit7 UPCL:
Programmable clear bit
This bit initializes the internal state of UART.
When this bit is set to "1":
⋅
Directly reset UART (software reset). In this case, the register settings
will be maintained. Note that any active transmission or reception will be
cut off immediately.
⋅
Baud rate generator restarts by reloading the setting value of the BGR1/0
register.
⋅
All the transmission and reception interrupt factors
(SSR:PE,FRE,ORE,RDRF,TDRE,TBI) are initialized(0000110
B
).
When this bit is set to "0": No effect.
A read always results in "0".
Notes:
⋅
Execute a programmable clear after disabling interrupts.
⋅
When using FIFO, disable FIFO (FCR0:FE2,FE1=0) before you execute
a programmable clear.
bit6,
bit5
Reserved bits
Read: The value is undefined.
Write: No effect
on operation.
bit4 RIE:
Reception interrupt enable
bit
⋅
This bit enables or disables the output of reception interrupt request to
the CPU.
⋅
When the RIE bit and reception data flag bit (SSR:RDRF) are set to "1",
or any of the error flag bit (SSR:PE, ORE, FRE) is set to "1", a reception
interrupt request will be output.
bit3 TIE:
Transmission interrupt
enable bit
⋅
This bit enables or disables the output of transmission interrupt request to
the CPU.
⋅
When the TIE bit and the SSR:TDRE bit are set to "1", a transmission
interrupt request will be output.
bit2 TBIE:
Transmission bus idle
interrupt enable bit
⋅
This bit enables or disables the output of transmission bus idle interrupt
request to the CPU.
⋅
When the TBIE bit and TBI bit are set to "1", a transmission bus idle
interrupt request will be output.
MB91520 Series
MN705-00010-1v0-E
1344