Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
332
8.3. I
2
C Master Mode
I
2
C master mode is shown.
In master mode, a start condition is generated on the I
2
C bus, which then receives the clock. If I
2
C bus is in
the idle state (SCL="H", SDA="H"), the master mode is selected when "1" is set to the MSS bit in the
IBCR register, and the ACT bit in the IBCR register becomes "1".
8.3.1. Start Condition Generation
A start condition is output if:
- When SDA="H", SCL="H", ISMK:EN="1", and IBSR:BB="0", "1" is written to the IBCR:MSS bit
If a start condition is output to I2C bus the IBCR:ACT bit is set to "1". Then, once the start condition is
received, the IBSR:BB bit is set to "1", indicating that I
2
C bus is on the communication. (See Figure 8-8)
Figure 8-8 Relationship between Start Condition Output and Various Bits
Start Condition
SDA A6 A5
SCL 1 2
BB bit
MSS bit
“1”write
ACT bit
TRX bit
FBT bit
TDRE bit
A6:address bit 6
A5:address bit 5
MB91520 Series
MN705-00010-1v0-E
1645