Fujitsu FR81S User Manual
CHAPTER 21: 32-BIT FREE-RUN TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
4.1.2. Timer Control Register (Lower Bit) : TCCSL
The bit configuration of timer control register (Lower bit) is shown.
This register is used to control the operation of the free-run timer.
TCCSL3-5 (Free-run timer 3-5): Address Base_addr+09
H
(Access: Byte,
Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
STOP
-
SCLR
CLK3
CLK2
CLK1
CLK0
Initial value
0
1
0
0
0
0
0
0
Attribute R0,WX
R/W
R0,WX
R0,W
R/W
R/W
R/W
R/W
[bit7] - : Undefined
The read value is always "0". This does not affect the writing operation.
[bit6] STOP : Timer enabled
STOP
Operation
0
Count enabled (operation)
1
Count disabled (stop)
⋅
The STOP bit is used to start/stop counting of the 32-bit free-run timer.
⋅
When the STOP bit is "0": Counter of the 32-bit free-run timer is started.
⋅
When the STOP bit is "1": Counter of the 32-bit free-run timer is stopped.
Note:
If output compare is in use, the output compare operation will stop when the free-run timer stops.
[bit5] - : Undefined
The read value is always "0". This does not affect the writing operation.
[bit4] SCLR : Timer clear
SCLR
State
Read
Write
0
The read value is always "0".
Writing "0" has no meaning.
1
Clears the free-run timer.
⋅
When this bit is set to "1", the count value of the free-run timer is cleared to "00000000
H
". The prescaler
within the macro is also cleared at this time.
⋅
The value read out is always "0".
Note:
If you set this bit to "1", timer clear will be performed at the next internal clock timing.
MB91520 Series
MN705-00010-1v0-E
809