Nortel Networks MSC8101 ADS User Manual
44
MSC8101ADS RevB User’s Manual
MOTOROLA
Functional Description
ceivers are disabled during access to that region, avoiding possible
A
contention over data lines.
The MSC8101 chip-selects assignment to the various memories / registers on the MSC8101ADS
are shown in
are shown in
5•6
Synchronous DRAM Bank
To enhance MSC8101ADS performance, 16MBytes of SDRAM is provided on the Unbuffered
PPC Bus for storage and fast data exchange. The SDRAM is configured as 2 X 2Meg X 32. Use
is done with two MT48LC2M32B2 chips by Micron or compatibles (Samsung). The part data sheet
may be obtained on the Internet at URL: http://www.micron.com/mti/msp/htm/datasheet.html.
PPC Bus for storage and fast data exchange. The SDRAM is configured as 2 X 2Meg X 32. Use
is done with two MT48LC2M32B2 chips by Micron or compatibles (Samsung). The part data sheet
may be obtained on the Internet at URL: http://www.micron.com/mti/msp/htm/datasheet.html.
Since it includes only 2 memory chips, the SDRAM is unbuffered from the MSC8101, avoiding the
delay associated with address and data buffers. As the volume of this sdram is far beyond any
possible future requirement, the SDRAM is soldered directly to the board.
delay associated with address and data buffers. As the volume of this sdram is far beyond any
possible future requirement, the SDRAM is soldered directly to the board.
In order to provide Host Interface held a half of the Data Bus (32bits of 64bits wide) width the DIP
switch array is present. It allows to shift address field by one bit A28->A29, A27->A28,.A12->A13.
In this case we can use one from two SDRAM chip, therewith the second chip will be disable with
BCSR’s control bit - memory space will be decreased by half. The system bus of the MSC8101 is
very fast and run up to 100MHz, therefore any type of logic for address mux puts large timing
penalty and impossible. The mux is done by jumper’s array. See
switch array is present. It allows to shift address field by one bit A28->A29, A27->A28,.A12->A13.
In this case we can use one from two SDRAM chip, therewith the second chip will be disable with
BCSR’s control bit - memory space will be decreased by half. The system bus of the MSC8101 is
very fast and run up to 100MHz, therefore any type of logic for address mux puts large timing
penalty and impossible. The mux is done by jumper’s array. See
The SDRAM’s timing is controlled by the 1’nd SDRAM machine of the MSC8101, which will be
E. When an unbuffered CS region is being accessed, buffers do not open anyway.
A. During read cycles.
A. During read cycles.
TABLE 5-3. MSC8101ADS Chip Select Assignments
Chip
Select
Assignment
Bus
Timing
Machine
CS0
Flash SIMM /BCSR Config Word
PPC (Buffered)
GPCM
CS1
BCSR
PPC (Buffered)
GPCM
CS2
SDRAM(soldered on the board)
PPC (Unbuffered)
SDRAM Machine 1
CS3
SDRAM spare (soldered on the
board)
PPC (Unbuffered)
SDRAM Machine 1
CS4
QFALC T1/E1
PPC (Buffered)
UPMB
CS5
ATM UNI Microprocessor I/F
PPC (Buffered)
GPCM
CS6
Communication Tool M/P Interface
CS1
PPC (Buffered)
GPCM/UPMA
a
a. User defined.
CS7
Communication Tool M/P Interface
CS2
PPC (Buffered)
GPCM/UPMA
CS10
DPSRAM
Internal Local PPC
UPMC
CS11
DSP Peripherals
Internal Local PPC
GPCM
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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