Intel 8XC251SQ User Manual

13-26

In this example, an 80C251SB operates in nonpage mode with a 16-bit external address bus in-
terfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM (Figure 13-25). The 80C251SB is con-
figured so that RD# is asserted for addresses 

≤

7F:FFFFH and PSEN# is asserted for addresses 

≥

80:0000H. Figure 13-26 shows two ways to address the external memory in the internal memory
space. 

Addressing external RAM locations in either region 00: or region 01: produces the same address
at the external bus pins. However, if the external EPROM and the external RAM require different
numbers of wait states, the external RAM must be addressed entirely in region 01:. Recall that
the number of wait states for region 01: is independent of the remaining regions and always have
the same number of wait states (see Table 4-3 on page 4-13) unless the real-time wait states are
selected (see Figure 13-11 on page 13-11).

The examples that follow illustrate two possibilities for addressing the external RAM.

If an application requires fast access to the stack, the stack can reside in the fast on-chip data
RAM (00:0020H–00:041FH) and, when necessary, roll out into the slower external RAM. See
the left side of Figure 13-26. In this case, the external RAM can have wait states only if the
EPROM has wait states. Otherwise, if the stack rolls out above location 00:041FH, the external
RAM would be accessed with no wait state.

If fast access to a block of data is more important than fast access to the stack, the data can be
stored in the on-chip data RAM, and the stack can be located entirely in external memory. If the
external RAM requires a different number of wait states than the EPROM, address the external
RAM entirely in region 01:. See the right side of Figure 13-26. Addresses above 00:041FH roll
out to external memory beginning at 0420H.