Intel Core 2 Duo U7500 U7500 User Manual
Product codes
U7500
Summary Tables of Changes
Specification Update
13
AL = Dual-Core Intel® Xeon® processor 7100 series
AN = Intel® Pentium® Dual-Core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® Dual-Core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AV = Intel® Core™2 Extreme processor QX9000 sequence and Intel® Core™2 Quad
AN = Intel® Pentium® Dual-Core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® Dual-Core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AV = Intel® Core™2 Extreme processor QX9000 sequence and Intel® Core™2 Quad
processor Q9000 sequence processor
AW = Intel® Core™ 2 Duo
AX =Quad-Core Intel® Xeon® processor 5400 series
AY =Dual-Core Intel® Xeon® processor 5200 series
AZ =Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm
AW = Intel® Core™ 2 Duo
AX =Quad-Core Intel® Xeon® processor 5400 series
AY =Dual-Core Intel® Xeon® processor 5200 series
AZ =Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm
process
Note: Intel processor numbers are not a measure of performance. Processor numbers
for details.
Steppings
Number
C-0 M-0
Status ERRATA
AZ1
X
X
No Fix
EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB
Shootdown
Shootdown
AZ2
X
X
No Fix
INVLPG Operation for Large (2M/4M) Pages May Be Incomplete
under Certain Conditions
under Certain Conditions
AZ3
X
X
No Fix
Store to WT Memory Data May Be Seen in Wrong Order by
Two Subsequent Loads
Two Subsequent Loads
AZ4
X
X
No Fix
Non-Temporal Data Store May Be Observed in Wrong Program
Order
Order
AZ5
X
X
No Fix
Page Access Bit May Be Set Prior to Signaling a Code Segment
Limit Fault
Limit Fault
AZ6
X
X
No Fix
Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code #PF
Invalidation May Result in Improper Handling of Code #PF
AZ7
X
X
No Fix
Storage of PEBS Record Delayed Following Execution of MOV
SS or STI
SS or STI
AZ8
X
X
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May
Not Count Some Transitions
Not Count Some Transitions
AZ9
X
X
No Fix
A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
Prevent Triggering of the Monitoring Hardware
AZ10
X
X
No Fix
Performance Monitoring Event MISALIGN_MEM_REF May Over
Count
Count
AZ11
X
X
No Fix
The Processor May Report a #TS Instead of a #GP Fault
AZ12
X
X
No Fix
Code Segment Limit Violation May Occur on 4-GB Limit Check