Intel Core 2 Duo U7500 U7500 User Manual
Product codes
U7500
Summary Tables of Changes
Specification Update
15
Steppings
Number
C-0 M-0
Status ERRATA
AZ34
X
X
Plan Fix
CPUID Reports Architectural Performance Monitoring Version 2
is Supported, When Only Version 1 Capabilities are Available
is Supported, When Only Version 1 Capabilities are Available
AZ35
X
X
No Fix
B0-B3 Bits in DR6 May Not Be Properly Cleared after Code
Breakpoint
Breakpoint
AZ36
X
X
No Fix
An xTPR Update Transaction Cycle, if Enabled, May Be Issued
to the FSB after the Processor Has Issued a Stop-Grant Special
Cycle
to the FSB after the Processor Has Issued a Stop-Grant Special
Cycle
AZ37
X
X
Plan Fix
Performance Monitoring Event IA32_FIXED_CTR2 May Not
Function Properly When Max Ratio Is a Non-Integer Core-to-
Bus Ratio
Function Properly When Max Ratio Is a Non-Integer Core-to-
Bus Ratio
AZ38
X
X
No Fix
Instruction Fetch May Cause a Livelock During Snoops of the
L1 Data Cache
L1 Data Cache
AZ39
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type May
Cause a System Hang or a Machine Check Exception
Cause a System Hang or a Machine Check Exception
AZ40
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead
to Memory-Ordering Violations
to Memory-Ordering Violations
AZ41
X
X
Plan Fix
VM Exit with Exit Reason "TPR Below Threshold" Can Cause the
Blocking by MOV/POP SS and Blocking by STI Bits to Be
Cleared in the Guest Interruptibility-State Field
Blocking by MOV/POP SS and Blocking by STI Bits to Be
Cleared in the Guest Interruptibility-State Field
AZ42
X
X
No Fix
Using Memory Type Aliasing with Cacheable and WC Memory
Types May Lead to Memory Ordering Violations
Types May Lead to Memory Ordering Violations
AZ43
X
X
No Fix
VM Exit Caused by a SIPI Results in Zero Being Saved to the
Guest RIP Field in the VMCS
Guest RIP Field in the VMCS
AZ44
X
X
No Fix
NMIs May Not Be Blocked by a VM-Entry Failure
AZ45
X
X
Plan Fix
Partial Streaming Load Instruction Sequence May Cause the
Processor to Hang
Processor to Hang
AZ46
X
X
Plan Fix
Self/Cross Modifying Code May Not Be Detected or May Cause
a Machine Check Exception
a Machine Check Exception
AZ47
X
X
Plan Fix
Data TLB Eviction Condition in the Middle of a Cacheline Split
Load Operation May Cause the Processor to Hang
Load Operation May Cause the Processor to Hang
AZ48
X
X
Plan Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
AZ49
X
X
Plan Fix
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
Processor Hang or Unexpected Instruction Execution Results
AZ50
X
X
No Fix
Benign Exception after a Double Fault May Not Cause a Triple-
Fault Shutdown
Fault Shutdown
AZ51
X
X
No Fix
LER MSRs May Be Incorrectly Updated
AZ52
X
X
Plan Fix
Processor May Unexpectedly Assert False THERMTRIP# After
Receiving a Warm Reset
Receiving a Warm Reset
AZ53
X
X
No Fix
Short Nested Loops That Span Multiple 16-Byte Boundaries
May Cause a Machine Check Exception or a System Hang
May Cause a Machine Check Exception or a System Hang