Intel Core 2 Duo U7500 U7500 User Manual
Product codes
U7500
Summary Tables of Changes
14
Specification
Update
Steppings
Number
C-0 M-0
Status ERRATA
AZ13
X
X
No Fix
A Write to an APIC Register Sometimes May Appear to Have
Not Occurred
Not Occurred
AZ14
X
X
No Fix
Last Branch Records (LBR) Updates May Be Incorrect after a
Task Switch
Task Switch
AZ15
X
X
No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
May Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
Crossing Page Boundaries with Inconsistent Memory Types
May Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
AZ16
X
X
No Fix
Upper 32 Bits of 'From' Address Reported through BTMs or
BTSs May Be Incorrect
BTSs May Be Incorrect
AZ17
X
X
No Fix
Address Reported by Machine-Check Architecture (MCA) on
Single-Bit L2 ECC Errors May Be Incorrect
Single-Bit L2 ECC Errors May Be Incorrect
AZ18
X
X
No Fix
Code Segment Limit/Canonical Faults on RSM May Be Serviced
before Higher Priority Interrupts/Exceptions
before Higher Priority Interrupts/Exceptions
AZ19
X
X
No Fix
Store Ordering May Be Incorrect between WC and WP Memory
Type
Type
AZ20
X
X
No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after
Shutdown
Shutdown
AZ21
X
X
No Fix
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
Handler Invocation
AZ22
X
X
No Fix
Performance Monitoring Events for Retired Instructions (C0H)
May Not Be Accurate
May Not Be Accurate
AZ23
X
X
No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May
Result in Unpredictable System Behavior
Result in Unpredictable System Behavior
AZ24
X
X
No Fix
CMPSB, LODSB, or SCASB in 64-Bit Mode with Count Greater
or Equal to 248 May Terminate Early
or Equal to 248 May Terminate Early
AZ25
X
X
No Fix
Writing the Local Vector Table (LVT) When an Interrupt Is
Pending May Cause an Unexpected Interrupt
Pending May Cause an Unexpected Interrupt
AZ26
X
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced before Higher Priority Interrupts
Serviced before Higher Priority Interrupts
AZ27
X
X
No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update
the Last Exception Record (LER) MSR
the Last Exception Record (LER) MSR
AZ28
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AZ29
X
X
No Fix
Split Locked Stores May Not Trigger the Monitoring Hardware
AZ30
X
X
No Fix
Programming the Digital Thermal Sensor (DTS) Threshold May
Cause Unexpected Thermal Interrupts
Cause Unexpected Thermal Interrupts
AZ31
X
X
No Fix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a Memory
Ordering Issue
without Proper Semaphores or Barriers May Expose a Memory
Ordering Issue
AZ32
X
X
No Fix
General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
Segment Limit Violation above 4-G Limit
AZ33
X
X
No Fix
An Asynchronous MCE during a Far Transfer May Corrupt ESP