Intel PCI User Manual

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IEEE 802.3x compliant flow control support

— Enables control of the transmission of Pause packets through software or hardware 

triggering

— Provides indications of receive FIFO status

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State-of-the-art internal transceiver (PHY) with DSP architecture implementation

— Digital adaptive equalization and crosstalk

— Echo and crosstalk cancellation

— Automatic MDI/MDI-X crossover at all speeds and compensation for cable length

— Media Independent Interfaces (MII) IEEE 802.3e for supporting 10/10BASE-T 

transceivers

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Integrated dual-port solution comprised of two distinct MAC/PHY instances (82546GB/EB)

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Provides on-chip IEEE 802.3z PCS SerDes functionality (82546GB/EB and 82545GM/EM)

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Receive and transmit IP and TCP/UDP checksum offloading capabilities

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Transmit TCP Segmentation (operating system support required)

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Packet filtering based on checksum errors

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Support for various address filtering modes:

— 16 exact matches (unicast, or multicast)

— 4096-bit hash filter for multicast frames

— Promiscuous, unicast and promiscuous multicast transfer modes

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IEEE 802.1q VLAN support

1

— Ability to add and strip IEEE 802.1q VLAN tags

— Packet filtering based on VLAN tagging, supporting 4096 tags

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SNMP and RMON statistic counters

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Support for IPv6 including (not applicable to the 82544GC/EI):

— IP/TCP and IP/UDP receive checksum offload

— Wake up filters

— TCP segmentation

1. Not applicable to the 82541ER.