Intel PCI User Manual
Introduction
Software Developer’s Manual
5
1.3.6
Manageability Features (Not Applicable to the 82544GC/EI or
82541ER)
•
Manageability support for ASF 1.0 and AoL 2.0 by way of SMBus 2.0 interface and either:
— TCO mode SMBus-based management packet transmit / receive support
— Internal ASF-compliant TCO controller
1.3.7
Additional Ethernet Controller Features
•
Implements ACPI
1
register set and power down functionality supporting D0 and D3 states
•
Supports Wake on LAN (WoL)
1
•
Provides four wire serial EEPROM interface for loading product configuration information
— Allows use of either 3.3 V dc or 5 V dc powered EEPROM
•
Provides external parallel interface for up to 512 KB of FLASH memory for support of Pre-
Boot Execution Environment (PXE)
Boot Execution Environment (PXE)
•
Provides seven general purpose user mode pins
•
Provides Activity and Link LED indications
•
Supports little-endian byte ordering for 32- and 64-bit systems
•
Provides loopback capabilities under TBI (82544GC/EI)
2
(internal SerDes for the 82546GB/
EB and 82545GM/EM) and GMII/MII modes of operation
•
Provides IEEE JTAG boundary scan support
•
Four programmable LED outputs (Not applicable to the 82544GC/EI).
— For the 82546GB/EB, four programmable LED outputs for each port
•
Detection and improved power-management with LAN cable unconnected (82546GB/EB)
1.3.8
Technology Features
•
Implemented in 0.15
µ CMOS process (0.13µ for the 82541xx and 82547GI/EI)
•
Packaged in 364 PBGA.
— For the 82544EI, packaged in 416 PBGA.
— For the 82540EP/EM, 82541xx, and 82547GI/EI, packaged in 196 PBGA.
•
Implemented in low power (3.3 V dc or 5 V dc compatible PCI signaling) CMOS process
1. Not applicable to the 82541ER.
2. Not applicable to the 82541xx, 82547GI/EI or 82540EP/EM.
2. Not applicable to the 82541xx, 82547GI/EI or 82540EP/EM.