Intel PCI User Manual
Software Developer’s Manual
367
Register Descriptions
Table 13-147. TDFH Register Bit Description)
13.8.7
Transmit Data FIFO Tail Register
TDFT (03418h; R/W)
This register stores the head of the Ethernet controller’s on–chip transmit data FIFO. Since the
internal FIFO is organized in units of 64-bit words, this field contains the 64-bit offset of the
internal FIFO is organized in units of 64-bit words, this field contains the 64-bit offset of the
current Transmit FIFO Tail. So a value of “8h” in this register corresponds to an offset of 8
quadwords into the Transmit FIFO space. This register is available for diagnostic purposes only,
and should not be written during normal operation.
and should not be written during normal operation.
Table 13-148. TDFT Register Bit Description
13.8.8
Transmit Data FIFO Head Saved Register
TDFHS (03420h; R/W)
This register stores a copy of the Transmit Data FIFO Head register in case the internal register
needs to be restored. This register is available for diagnostic purposes only, and should not be
written during normal operation.
written during normal operation.
31
11 10
0
Reserved
FIFO Head
Field
Bit(s)
Initial
Value
Value
Description
FIFO Head
10:0
0b
Transmit FIFO Head pointer.
Reserved
31:11
0b
Reads as 0b. Should be written to 0b for future compatibility.
31
11 10
0
Reserved
FIFO Tail
Field
Bit(s)
Initial
Value
Value
Description
FIFO Tail
10:0
0b
Transmit FIFO tail pointer.
Reserved
31:11
0b
Reads as 0b. Should be written to 0b for future compatibility.