Intel PCI User Manual
Software Developer’s Manual
369
Register Descriptions
Table 13-151. TDFPC Register Bit Description
13.8.11
Packet Buffer Memory
PBM (10000h - 1FFFCh; R/W)
All PBM (FIFO) data is available to diagnostics. Locations can be accessed as 32-bit or 64-bit
words. The internal PBM is 64 KB (40 KB for the 82547GI/EI) in size. Software can configure the
amount of PBM space that is used as the transmit FIFO versus the receive FIFO. The default is 16
amount of PBM space that is used as the transmit FIFO versus the receive FIFO. The default is 16
KB of transmit FIFO space and 48 KB of receive FIFO space. For the 82547GI/EI, the default is
18 KB of transmit FIFO space and 22 KB of receive FIFO space.
Regardless of the individual FIFO sizes that software configures, the RX FIFO is located first in
the memory mapped PBM space. So for the default FIFO configuration, the RX FIFO occupies
the memory mapped PBM space. So for the default FIFO configuration, the RX FIFO occupies
offsets 10000h - 1BFFFh of the memory mapped space, while the TX FIFO occupies offsets
1C000h - 1FFFFh of the memory mapped space.
Table 13-152. PBM Bit Description
31
13 12
0
Reserved
FIFO Tail
Field
Bit(s)
Initial
Value
Value
Description
FIFO Tail
12:0
0b
The number of packets to be transmitted that are currently in
the TX FIFO.
the TX FIFO.
Reserved
31:13
0b
Reads as 0b. Should be written to 0b for future compatibility.
31
0
FIFO Data
Field
Bit(s)
Initial
Value
Value
Description
FIFO Data
31:0
0b
Packet Buffer Data