Intel PCI User Manual

372

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PHY Reset (CTRL.PHY_RST) should be set to 0b. Setting this bit to 1b resets the PHY 
without accessing the PHY registers. This bit is ignored in internal SerDes mode.

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CTRL.ILOS should be set to 0b (not applicable to the 82541xx and 82547GI/EI).

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If Flow Control is desired, program the FCAH, FCAL, FCT and FCTTV registers. If not, they 
should be written with 0b. To enable XON frame transmission, the XON Enable 

(FCTRL.XONE) bit must be set. Advertising Flow Control capabilities during the Auto-

Negotiation process is dependent on whether the Ethernet controller is operating in internal 
SerDes or internal PHY mode. In internal SerDes mode, the TXCW register must be set up 

prior to starting the Auto-Negotiation process. In internal PHY mode, the appropriate PHY 

registers must be set up properly to advertise desired capabilities prior to starting or re-starting 
the Auto-Negotiation process. The Receive Flow Control Enable (CTRL.RFCE) and Transmit 

Flow Control Enable (CTRL.TFCE) bits need to be explicitly set by software in internal PHY 

mode (because Auto-Negotiation is managed by PHY rather than the MAC), or when a fiber 
connection is desired but link was forced rather than Auto-Negotiated.

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If VLANs are not used, software should clear VLAN Mode Enable (CTRL.VME) bit. In this 

instance, there is no need then to initialize the VLAN Filter Table Array (VFTA). If VLANs 
are desired, the VFTA should be both initialized and loaded with the desired information.

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For the 82541xx and 82547GI/EI, clear all statistical counters.

Program the Receive Address Register(s) (RAL/RAH) with the desired Ethernet addresses. 

RAL[0]/RAH[0] should always be used to store the Individual Ethernet MAC address of the 
Ethernet controller. This can come from the EEPROM or from any other means (for example, on 

some machines, this comes from the system PROM not the EEPROM on the adapter port).

Initialize the MTA (Multicast Table Array) to 0b. Per software, entries can be added to this table as 

desired.

Program the Interrupt Mask Set/Read (IMS) register to enable any interrupt the software driver 
wants to be notified of when the event occurs. Suggested bits include RXT, RXO, RXDMT, 

RXSEQ, and LSC. There is no immediate reason to enable the transmit interrupts.

If software uses the Receive Descriptor Minimum Threshold Interrupt, the Receive Delay Timer 
(RDTR) register should be initialized with the desired delay time.

Allocate a region of memory for the receive descriptor list. Software should insure this memory is 

aligned on a paragraph (16-byte) boundary. Program the Receive Descriptor Base Address 

(RDBAL/RDBAH) register(s) with the address of the region. RDBAL is used for 32-bit addresses 
and both RDBAL and RDBAH are used for 64-bit addresses.

Set the Receive Descriptor Length (RDLEN) register to the size (in bytes) of the descriptor ring. 

This register must be 128-byte aligned.

The Receive Descriptor Head and Tail registers are initialized (by hardware) to 0b after a power-on 

or a software-initiated Ethernet controller reset. Receive buffers of appropriate size should be 
allocated and pointers to these buffers should be stored in the receive descriptor ring. Software 

initializes the Receive Descriptor Head (RDH) register and Receive Descriptor Tail (RDT) with the 

appropriate head and tail addresses. Head should point to the first valid receive descriptor in the 
descriptor ring and tail should point to one descriptor beyond the last valid descriptor in the 

descriptor ring.