Intel PCI User Manual

371

This section lists all necessary initializations and describes the reset commands for the PCI/PCI-X 

Family of Gigabit Ethernet Controllers.

TBI mode is used by the 82544GC/EI. Internal SerDes is used by the 82546GB/EB and 

.

At power up, the Ethernet controller is not automatically configured by the hardware for normal 
operation. Software initialization is required before normal operation can continue. In general, the 

Ethernet controller is considered non-functional until the software driver successfully loads and 

sets up the hardware. However, Auto-Negotiation can start at power up or upon receipt of an 
assertion of PCI reset if configured to do so by the EEPROM.

Several values in the Device Control Register (CTRL) need to be set upon power up or after an 

Ethernet controller reset for normal operation.

•

Speed and duplex are determined via Auto-Negotiation by the PHY, Auto-Negotiation by the 
MAC for internal SerDes

1

 mode, or forced by software if the link is forced. In internal PHY 

mode, the Ethernet controller can be configured automatically by hardware or forced by 
software to the same configuration as the PHY.

•

In internal PHY mode, the Auto-Speed Detection Enable (CTRL.ASDE) bit, when set to 1b, 

detects the resolved speed and duplex of the link and self-configure the MAC appropriately. 
This bit should be set in conjunction with the Set Link Up (CTRL.SLU) bit.

•

The MAC can also be forced to a specific Speed/Duplex combination. This is accomplished by 

setting the Set Link Up (CTRL.SLU), Force Speed (CTRL. FRCSPD) and Force Duplex 
(CTRL.FRCDPLX) bits. Once speed and duplex are determined (either via Auto-Negotiation 

or forced by software), speed is forced by setting the appropriate Speed Selection 

(CTRL.SPEED) bits and duplex is forced by updating the Full Duplex (CTRL.FD) bit.

•

For the 82541xx and 82547GI/EI, configure the LED behavior through LEDCTRL.

•

Link Reset (CTRL.LRST) should be set to 0b (normal). The Ethernet controller defaults to 

LRST = 1b which disables Auto-Negotiation. A transition to 0b initiates the Auto-Negotiation 
function. LRST can be defined in the EEPROM. This bit is only valid in internal SerDes mode 

and has no effect in internal PHY mode.

1.

The 82540EP/EM, 82541xx, and 82547GI/EI do not support any SerDes functionality.