Intel PCI User Manual

373

Program the Receive Control (RCTL) register with appropriate values for desired operation to 
include the following:

•

Set the receiver Enable (RCTL.EN) bit to 1b for normal operation. However, it is best to leave 

the Ethernet controller receive logic disabled (RCTL.EN = 0b) until after the receive 
descriptor ring has been initialized and software is ready to process received packets.

•

Set the Long Packet Enable (RCTL.LPE) bit to 1b when processing packets greater than the 

standard Ethernet packet size. For example, this bit would be set to 1b when processing Jumbo 
Frames.

•

Loopback Mode (RCTL.LBM) should be set to 00b for normal operation.

•

Configure the Receive Descriptor Minimum Threshold Size (RCTL.RDMTS) bits to the 
desired value.

•

Configure the Multicast Offset (RCTL.MO) bits to the desired value.

•

Set the Broadcast Accept Mode (RCTL.BAM) bit to 1b allowing the hardware to accept 
broadcast packets.

•

Configure the Receive Buffer Size (RCTL.BSIZE) bits to reflect the size of the receive buffers 

software provides to hardware. Also configure the Buffer Extension Size (RCTL.BSEX) bits if 
receive buffer needs to be larger than 2048 bytes.

•

Set the Strip Ethernet CRC (RCTL.SECRC) bit if the desire is for hardware to strip the CRC 

prior to DMA-ing the receive packet to host memory.

•

For the 82541xx and 82547GI/EI, program the Interrupt Mask Set/Read (IMS) register to 

enable any interrupt the driver wants to be notified of when the even occurs. Suggested bits 

include RXT, RXO, RXDMT, RXSEQ, and LSC. There is no immediate reason to enable the 
transmit interrupts. Plan to optimize interrupts later, including programming the interrupt 

moderation registers TIDV, TADV, RADV and IDTR.

•

For the 82541xx and 82547GI/EI, if software uses the Receive Descriptor Minimum 
Threshold Interrupt, the Receive Delay Timer (RDTR) register should be initialized with the 

desired delay time.

Allocate a region of memory for the transmit descriptor list. Software should insure this memory is 
aligned on a paragraph (16-byte) boundary. Program the Transmit Descriptor Base Address 

(TDBAL/TDBAH) register(s) with the address of the region. TDBAL is used for 32-bit addresses 

and both TDBAL and TDBAH are used for 64-bit addresses.

Set the Transmit Descriptor Length (TDLEN) register to the size (in bytes) of the descriptor ring. 
This register must be 128-byte aligned.

The Transmit Descriptor Head and Tail (TDH/TDT) registers are initialized (by hardware) to 0b 

after a power-on or a software initiated Ethernet controller reset. Software should write 0b to both 

these registers to ensure this.

Initialize the Transmit Control Register (TCTL) for desired operation to include the following:

•

Set the Enable (TCTL.EN) bit to 1b for normal operation.

•

Set the Pad Short Packets (TCTL.PSP) bit to 1b.