Renesas R5S72621 User Manual

 
Section 34   User Debugging Interface 

Page 1820 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

Serial data input/output 
clock pin 

TCK 

Input 

Data is serially supplied to this module from the 
data input pin (TDI), and output from the data 
output pin (TDO), in synchronization with this clock.

Mode select input pin 

TMS 

Input 

The state of the TAP control circuit is determined 
by changing this signal in synchronization with 
TCK. The protocol complies with the JTAG 
standard (IEEE Std.1149.1). 

Reset input pin 

TRST 

Input 

Input is accepted asynchronously with respect to 
TCK, and when low, this module is reset. 

TRST 

must be low for a period when power is turned on 
regardless of using the function. See section 
34.4.2, Reset Configuration, for more information. 

Serial data input pin 

TDI 

Input 

Data is transferred to this module by changing this 
signal in synchronization with TCK. 

Serial data output pin 

TDO 

Output Data is read from this module by reading this pin in 

synchronization with TCK. The initial value of the 
data output timing is the TCK falling edge, but this 
initial value can be changed to the TCK rising edge 
by inputting the TDO transition timing switching 
command to SDIR. See section 34.4.3, TDO 
Output Timing, for more information. 

ASE mode select pin 

ASEMD* Input 

If a low level is input at the 

ASEMD pin while the 

RES pin is asserted, ASE mode is entered; if a high 
level is input, product chip mode is entered. In ASE 
mode, dedicated emulator function can be used. 
The input level at the 

ASEMD pin should be held 

for at least one cycle after 

RES negation. 

Note:  *  When the emulator is not in use, fix this pin to the high level.