Renesas R5S72621 User Manual
Section 34 User Debugging Interface
R01UH0134EJ0400 Rev. 4.00
Page 1821 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
34.3
Description of the Emulation Command Registers
To use emulation commands, enter the emulation enable command in SDENR. The following
registers are provided for emulation.
registers are provided for emulation.
Table 34.2 Register Configuration for Emulation
Register Name
Abbreviation
R/W
Initial Value
Address
Access
Size
Size
Bypass register
SDBPR
Instruction register
SDIR
R
H'EFFD
H'FFFE2000
16
Enable register
SDENR
H'4
34.3.1
Bypass Register (SDBPR)
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDENR or SDIR is set to
BYPASS mode, SDBPR is connected between pins TDI and TDO pins. The initial value is
undefined.
BYPASS mode, SDBPR is connected between pins TDI and TDO pins. The initial value is
undefined.
34.3.2
Instruction Register (SDIR)
SDIR is a 16-bit read-only register. To use this register, the emulation enable command should be
set in SDENR. This register is initialized by
set in SDENR. This register is initialized by
TRST assertion or in the TAP test-logic-reset state.
This module can write to this register regardless of the CPU mode. When a reserved command is
set in this register, the operation is not guaranteed. The initial value is H'EFFD.
set in this register, the operation is not guaranteed. The initial value is H'EFFD.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Note:
The initial value of TI[7:0] is a reserved value, but replace it with a non-reserved value when setting a command.
*
1*
1*
1*
0*
1*
1*
1*
1*
1
1
1
1
1
1
0
1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TI[7:0]
-
-
-
-
-
-
-
-
Bit Bit
Name
Initial
Value
Value
R/W Description
15 to 8
TI[7:0]
11101111* R
Test Instruction
The instruction of this module is transferred to SDIR as
a serial input from TDI.
a serial input from TDI.
For commands, see table 34.3.