Renesas R5S72621 User Manual

 

 

Section 11   Multi-Function Timer Pulse Unit 2 
 

Page 506 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

0 WRE  0  R/(W) 

Initial Output Suppression Enable 

Selects the waveform output when synchronous 
counter clearing occurs in complementary PWM mode. 
The initial output is suppressed only when synchronous 
clearing occurs within the Tb interval at the trough in 
complementary PWM mode. When synchronous 
clearing occurs outside this interval, the initial value 
specified in TOCR is output regardless of the WRE bit 
setting. The initial value is also output when 
synchronous clearing occurs in the Tb interval at the 
trough immediately after TCNT_3 and TCNT_4 start 
operation. 

For the Tb interval at the trough in complementary 
PWM mode, see figure 11.40. 

0: Outputs the initial value specified in TOCR 

1: Suppresses initial output 

[Setting condition] 
  When 1 is written to WRE after reading WRE = 0 

Note:  *  Do not set to 1 when complementary PWM mode is not selected. 

 

The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle 
buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), 
timer A/D converter start request control register (TADCR), timer A/D converter start request 
cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers 
(TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-
bit read/write is not possible. Always access in 16-bit units.  

All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 
16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.