Intel Xeon E7420 AD80583QH0468M Data Sheet

Intel® Xeon® Processor 7400 Series Datasheet

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Most Intel® Xeon® Processor 7400 Series FSB signals use Assisted Gunning 
Transceiver Logic (AGTL+) signaling technology. This technology provides improved 
noise margins and reduced ringing through low voltage swings and controlled edge 
rates.

 

AGTL+ buffers are open-drain and require pull-up resistors to provide the high 

logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the 
addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the 
first clock of a low-to-high voltage transition. Platforms implement a termination 
voltage level for AGTL+ signals defined as V

TT

. Because platforms implement separate 

power planes for each processor (and chipset), V

CC

 and V

TT 

are supplied separately to 

the processor. This configuration allows for improved noise tolerance as processor 
frequency increases. Speed enhancements to data and address buses have made 
signal integrity considerations and platform design methods even more critical than 
with previous processor families. Design guidelines for the processor FSB are detailed 
in the appropriate platform design guidelines (refer to 

The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, 
GTLREF_ADD_MID and GTLREF_ADD_END) which are used by the receivers to 
determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and 
GTLREF_DATA_END are used for the 4X front side bus signaling group and 
GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front 
side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END, 
GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See 

 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID and 

GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines 
for details. Termination resistors (R

TT

) for AGTL+ signals are provided on the processor 

silicon and are terminated to V

TT

. The on-die termination resistors are always enabled 

on the processor to control reflections on the transmission line. Intel chipsets also 
provide on-die termination, thus eliminating the need to terminate the bus on the 
baseboard for most AGTL+ signals.

Some FSB signals do not include on-die termination (R

TT

) and must be terminated on 

the baseboard. See 

 for details regarding these 

signals.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for 
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog 
signal simulation of the FSB, including trace lengths, is highly recommended when 
designing a system. Contact your Intel Field Representative to obtain the processor 
signal integrity models, which includes buffer and package models.