Intel Xeon E7420 AD80583QH0468M Data Sheet
Product codes
AD80583QH0468M
Intel® Xeon® Processor 7400 Series Datasheet
17
Electrical Specifications
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details
of operation at core frequencies lower than the maximum rated processor speed.
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details
of operation at core frequencies lower than the maximum rated processor speed.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are
provided in
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are
provided in
, respectively. These specifications must be met
while also meeting signal integrity requirements as outlined in
. The
processor utilizes differential clocks. Details regarding BCLK[1:0] driver specifications
are provided in the CK410B Clock Synthesizer/Driver Design Guidelines.
are provided in the CK410B Clock Synthesizer/Driver Design Guidelines.
contains processor core frequency to FSB multipliers and their corresponding core
frequencies.
frequencies.
Notes:
1.
Individual processors operate only at or below the frequency marked on the package.
2.
For valid processor core frequencies, refer to the Intel® Xeon® Processor 7400 Series Specification
Update.
2.3.1
Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs, and are used to select the FSB frequency.
Please refer to
processor. BSEL[2:0] are CMOS outputs, and are used to select the FSB frequency.
Please refer to
defines the possible
combinations of the signals and the frequency associated with each combination. The
frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB
agents must operate at the same core and FSB frequency. See the appropriate platform
design guidelines for further details.
frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB
agents must operate at the same core and FSB frequency. See the appropriate platform
design guidelines for further details.
Table 2-1.
Core Frequency to Multiplier Configuration
Core Frequency to FSB
Multiplier
Core Frequency with
266 MHz FSB Clock
Notes
1/8
2.13 GHz
1/9
2.40 GHz
1/10
2.66 GHz
Table 2-2.
BSEL[2:0] Frequency Table
BSEL2
BSEL1
BSEL0
Bus Clock Frequency
0
0
0
266.666 MHz
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved