Intel Xeon E7420 AD80583QH0468M Data Sheet
Product codes
AD80583QH0468M
Electrical Specifications
16
Intel® Xeon® Processor 7400 Series Datasheet
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage (C
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage (C
BULK
), such as electrolytic capacitors,
supply current during longer lasting changes in current demand by the component,
such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition. Care must be taken in the
baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in
such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition. Care must be taken in the
baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in
. Failure to do so can result in timing violations or
reduced lifetime of the component. For further information and guidelines, refer to the
appropriate platform design guidelines.
appropriate platform design guidelines.
2.2.1
V
CC
Decoupling
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR). Bulk decoupling must be provided on the baseboard to handle large
current swings. The power delivery solution must insure the voltage and current
specifications are met (as defined in
Resistance (ESR). Bulk decoupling must be provided on the baseboard to handle large
current swings. The power delivery solution must insure the voltage and current
specifications are met (as defined in
). For further information regarding
power delivery, decoupling and layout guidelines, refer to the appropriate platform
design guidelines.
design guidelines.
2.2.2
V
TT
Decoupling
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
2.2.3
Front Side Bus AGTL+ Decoupling
The processor integrates signal termination on the die, as well as a portion of the
required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the FSB. Bulk decoupling must also be provided by
the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in
the appropriate platform design guidelines.
required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the FSB. Bulk decoupling must also be provided by
the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in
the appropriate platform design guidelines.
2.3
Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] inputs directly controls the FSB interface speed as well as the core
frequency of the processor. As in previous processor generations, the processor core
frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is
set during manufacturing. The default setting is for the maximum speed of the
processor. It is possible to override this setting using software. This permits operation
at lower frequencies than the processor’s tested frequency.
frequency of the processor. As in previous processor generations, the processor core
frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is
set during manufacturing. The default setting is for the maximum speed of the
processor. It is possible to override this setting using software. This permits operation
at lower frequencies than the processor’s tested frequency.