Intel Core™ i7-860 Processor (8M Cache, 2.80 GHz) BX8060517860 User Manual
Product codes
BX8060517860
Register Description
78
Datasheet
2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS
MC_CHANNEL_1_EW_BGF_SETTINGS
MC_CHANNEL_2_EW_BGF_SETTINGS
These are the parameters used to set the early warning RX clock crossing BGF.
2.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS
MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS
MC_CHANNEL_2_EW_BGF_OFFSET_SETTINGS
These are the parameters to set the early warning RX clock crossing BGF.
2.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY
MC_CHANNEL_1_ROUND_TRIP_LATENCY
MC_CHANNEL_2_ROUND_TRIP_LATENCY
These are the parameters to set the early warning RX clock crossing the Bubble
Generator FIFO (BGF) used to go between different clocking domains. These settings
provide the gearing necessary to make that clock crossing.
Generator FIFO (BGF) used to go between different clocking domains. These settings
provide the gearing necessary to make that clock crossing.
Device:
4, 5, 6
Function: 0
Offset:
CCh
Access as a Dword
Bit
Type
Reset
Value
Description
15:8
RW
1
ALIENRATIO. Dclk to Bclk ratio. Early warning Alien Ratio setting.
Device:
4, 5, 6
Function: 0
Offset:
D0h
Access as a Dword
Bit
Type
Reset
Value
Description
15:8
RW
2
EVENOFFSET. Early warning even offset setting.
7:0
RW
0
ODDOFFSET. Early warning odd offset setting.
Device:
4, 5, 6
Function: 0
Offset:
D4h
Access as a Dword
Bit
Type
Reset
Value
Description
7:0
RW
0
ROUND_TRIP_LATENCY.
Round trip latency for reads. Units are in UCLK. This register must be
Round trip latency for reads. Units are in UCLK. This register must be
programmed with the appropriate time for read data to be retuned from the
pads after a READ CAS is sent to the DIMMs.