Intel Core™ i7-860 Processor (8M Cache, 2.80 GHz) BX8060517860 User Manual

Product codes
BX8060517860
Page of 98
Datasheet
79
Register Description
2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1
MC_CHANNEL_1_PAGETABLE_PARAMS1
MC_CHANNEL_2_PAGETABLE_PARAMS1
These are the parameters used to control parameters for page closing policies..
2.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2
MC_CHANNEL_1_PAGETABLE_PARAMS2
MC_CHANNEL_2_PAGETABLE_PARAMS2
These are the parameters used to control parameters for page closing policies..
Device:
4, 5, 6
Function: 0
Offset:
D8h
Access as a Dword
Bit
Type
Reset
Value
Description
15:8
RW
0
REQUESTCOUNTER
This field is the upper 8 MSBs of a 12-bit counter. This counter determines the 
window over which the page close policy is evaluated.
7:0
RW
0
ADAPTIVETIMEOUTCOUNTER. 
This field is the upper 8 MSBs of a 12-bit counter. This counter adapts the 
interval between assertions of the page close flag. For a less aggressive page 
close, the length of the count interval is increased and vice versa for a more 
aggressive page close policy.
Device:
4, 5, 6
Function: 0
Offset:
DCh
Access as a Dword
Bit
Type
Reset
Value
Description
27
RW
0
ENABLEADAPTIVEPAGECLOSE
1 = Enables Adaptive Page Closing.
26:18
RW
0
MINPAGECLOSELIMIT
This field is the upper 9 MSBs of a 13-bit threshold limit. When the mistake 
counter falls below this threshold, a less aggressive page close interval (larger) 
is selected.
17:9
RW
0
MAXPAGECLOSELIMIT
This field is the upper 9 bits of a 13-bit threshold limit. When the mistake 
counter exceeds this threshold, a more aggressive page close interval (smaller) 
is selected.
8:0
RW
0
MISTAKECOUNTER. 
This field is the upper 8 MSBs of a 12-bit counter. This counter adapts the 
interval between assertions of the page close flag. For a less aggressive page 
close, the length of the count interval is increased and vice versa for a more 
aggressive page close policy.