Intel Xeon X3460 BX80605X3460 User Manual

104

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

The PCI Express Capability List register enumerates the PCI Express Capability 
structure in the PCI 3.0 configuration space.

The PCI Express Capabilities register identifies the PCI Express device type and 
associated capabilities.

7:0

RO

 0

Next Ptr
This field contains the offset to the next PCI Capability structure.

15:14

RV

0h

13:9

RO

00h

Interrupt Message Number
This field indicates the interrupt message number that is generated for 

PM/HP/BW-change events. When there are more than one MSI interrupt 

Number, this register field is required to contain the offset between the base 

Message Data and the MSI Message that is generated when the associated 

status bits in this capability register are set. IIO assigns the first vector for 

PM/HP/BW-change events and so this field is set to 0.

8

RO

0

Slot Implemented
0 = indicates no slot is connected to this port.

1 = indicates that the PCI Express link associated with the port is connected 

to a slot.

This register bit is of type “write once” and is controlled by BIOS/special 

initialization firmware.

7:4

RO

 1001b

Device/Port Type
This field identifies the type of device. It is set to 0100 for all the Express ports 

and 1001 for the DMA, Perfmon and PCI Express DF* register devices.

3:0

RO

2h

Capability Version
This field identifies the version of the PCI Express capability structure. Set to 

2h for PCI Express and DMA devices for compliance with the extended base 

registers.