Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Processor Integrated I/O (IIO) Configuration Registers
106
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.4.3.5
DEVCTRL—PCI Express Device Control Register
The PCI Express Device Control register controls PCI Express specific capabilities
parameters associated with the device.
parameters associated with the device.
(Sheet 1 of 2)
Device:
8
Function: 0, 1, 2
Offset:
48h
Bit
Attr
Default
Description
15
RO
0h
Reserved
14:12
RO
000
Max_Read_Request_Size
Express/DMI ports in Integrated I/O do not generate requests greater than
Express/DMI ports in Integrated I/O do not generate requests greater than
128B and this field is ignored.
11
RO 0
Enable No Snoop
Not applicable to root ports since they never set the ‘No Snoop’ bit for
Not applicable to root ports since they never set the ‘No Snoop’ bit for
transactions they originate (not forwarded from peer) to PCI Express.
This bit has no impact on forwarding of NoSnoop attribute on peer requests.
This bit has no impact on forwarding of NoSnoop attribute on peer requests.
10
RO
0
Reserved
9
RO
0
Reserved
8
RO
0h
Extended Tag Field Enable
This bit enables the PCI Express port/DMI to use an 8-bit Tag field as a
This bit enables the PCI Express port/DMI to use an 8-bit Tag field as a
requester.
7:5
RO
000
Max Payload Size
This field is set by configuration software for the maximum TLP payload size
This field is set by configuration software for the maximum TLP payload size
for the PCI Express port. As a receiver, the Integrated I/O must handle TLPs
as large as the set value. As a requester (that is, for requests where
Integrated I/O’s own RequesterID is used), it must not generate TLPs
exceeding the set value. Permissible values that can be programmed are
indicated by the Max_Payload_Size_Supported in the Device Capabilities
register:
000 = 128B max payload size
001 = 256B max payload size (applies only to standard PCI Express ports
000 = 128B max payload size
001 = 256B max payload size (applies only to standard PCI Express ports
and other devices alias to 128B)
others = alias to 128B
others = alias to 128B
4
RO
0
Enable Relaxed Ordering
Not applicable to root ports since they never set relaxed ordering bit as a
Not applicable to root ports since they never set relaxed ordering bit as a
requester (this does not include Tx forwarded from peer devices).
This bit has no impact on forwarding of relaxed ordering attribute on peer
This bit has no impact on forwarding of relaxed ordering attribute on peer
requests.
3
RO
0
Unsupported Request Reporting Enable
Applies only to the PCI Express/DMI ports. This bit controls the reporting of
Applies only to the PCI Express/DMI ports. This bit controls the reporting of
unsupported requests that Integrated I/O itself detects on requests its
receives from a PCI Express/DMI port.
0 = Reporting of unsupported requests is disabled.
0 = Reporting of unsupported requests is disabled.
1 = Reporting of unsupported requests is enabled.
Refer to the latest PCI Express Base Specification for complete details of how
Refer to the latest PCI Express Base Specification for complete details of how
this bit is used in conjunction with other bits to UR errors.
2
RO
0
Fatal Error Reporting Enable
Applies only to the PCI Express/DMI ports. Controls the reporting of fatal
Applies only to the PCI Express/DMI ports. Controls the reporting of fatal
errors that Integrated I/O detects on the PCI Express/DMI interface.
0 = Reporting of Fatal error detected by device is disabled.
0 = Reporting of Fatal error detected by device is disabled.
1 = Reporting of Fatal error detected by device is enabled.
Refer to the latest PCI Express Base Specification for complete details of how
Refer to the latest PCI Express Base Specification for complete details of how
this bit is used in conjunction with other bits to report errors.
For the PCI Express/DMI ports, this bit is not used to control the reporting of
For the PCI Express/DMI ports, this bit is not used to control the reporting of
other internal component uncorrectable fatal errors (at the port unit) in any
way.