Intel Xeon 7130N LF80550KF0878M Data Sheet
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Product codes
LF80550KF0878M
Features
92
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
7.4.9.4
Cache Data
This section contains cache-related data.
7.4.9.4.1
L2 Cache Size
Offset 27 - 28h is the L2 cache size field. The field reflects the size of the level two cache for each
core in kilobytes.
core in kilobytes.
Example: The Dual-Core Intel Xeon processor 7000 series may have a 2 MB (2048 KB) L2 cache
per core. Thus, offset 27 - 28h will contain 800h.
per core. Thus, offset 27 - 28h will contain 800h.
7.4.9.4.2
L3 Cache Size
Offset 29 - 2Ah is the L3 cache size field. The field reflects the size of the level three cache in
kilobytes.
kilobytes.
Example: The Dual-Core Intel Xeon processor 7000 series does not have an L3 cache per core.
Thus, offset 29 - 2Ah will contain 0h.
Thus, offset 29 - 2Ah will contain 0h.
7.4.9.4.3
Cache Voltage
There are two areas defined in the PIROM for the L3 cache voltages associated with the processor.
Offset 2B - 2Ch is the Processor Cache VID (Cache Voltage Identification), or CVID, field and
contains the voltage requested via the CVID pins. Because the Dual-Core Intel Xeon processor
7000 series does not have an L3 cache, this field is set to 0h. This field is in mV and is reflected in
hex. Some systems read this offset to determine if all processors support the same default CVID
setting.
Offset 2B - 2Ch is the Processor Cache VID (Cache Voltage Identification), or CVID, field and
contains the voltage requested via the CVID pins. Because the Dual-Core Intel Xeon processor
7000 series does not have an L3 cache, this field is set to 0h. This field is in mV and is reflected in
hex. Some systems read this offset to determine if all processors support the same default CVID
setting.
Minimum L3 cache voltage specifications are reflected in offset 2D - 2Eh. This field is in mV and
reflected in hex. For processors that follow a load line DC specification, the minimum V
reflected in hex. For processors that follow a load line DC specification, the minimum V
CACHE
reflected in this field should reflect the minimum allowable voltage at maximum current.
Example: Since the Dual-Core Intel Xeon processor 7000 series does not have an L3 cache, offset
2B - 2Ch would contain 0h and offset 2D - 2Eh would contain 0h.
2B - 2Ch would contain 0h and offset 2D - 2Eh would contain 0h.
7.4.9.5
Package Data
This section describes the package revision location at offset 32 - 35h. This field tracks the highest
level revision. It is provided in ASCII format of four characters (8 bits x 4 characters = 32 bits).
The package is documented as 1.0, 2.0, etc. Because this only consumes three ASCII characters, a
leading space is provided in the data field.
level revision. It is provided in ASCII format of four characters (8 bits x 4 characters = 32 bits).
The package is documented as 1.0, 2.0, etc. Because this only consumes three ASCII characters, a
leading space is provided in the data field.
Example: The C-1 stepping of the Intel Xeon processor with 512 KB L2 cache is packaged in the
603-pin micro-PGA interposer with 31 mm OLGA package and utilizes the second revision of this
package. Thus, at offset 32-35h the data is a space followed by 2.0. In hex, this would be 20, 32,
2E, 30.
603-pin micro-PGA interposer with 31 mm OLGA package and utilizes the second revision of this
package. Thus, at offset 32-35h the data is a space followed by 2.0. In hex, this would be 20, 32,
2E, 30.
7.4.9.6
Part Number Data
This section provides traceability. There are 208 available bytes in this section for future use.