Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
102
Datasheet
Bit Access Default
Value
RST/
PWR
Description
1 RO 1b Core
Link Type (LTYP):
Indicates that the link points to configuration
space of the integrated device, which controls
the x16 root port. The link address specifies
Indicates that the link points to configuration
space of the integrated device, which controls
the x16 root port. The link address specifies
the configuration address (segment, bus,
device, function) of the target root port.
device, function) of the target root port.
0 RWO 0b Core
Link Valid (LV):
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
1.8.5
EPLE2A - EP Link Entry 2 Address
B/D/F/Type: 0/0/0/PXPEPBAR
Address Offset:
68-6Fh
Default Value:
0000000000008000h
Access:
RO;
Size: 64
bits
Second part of a Link Entry which declares an internal link to another Root Complex
Element.
Element.
Bit Access Default
Value
RST/
PWR
Description
63:28 RO
00000000
0h
Core
Reserved for Configuration Space Base
Address ():
Not required if root complex has only one config
space.
Address ():
Not required if root complex has only one config
space.
27:20 RO
00h Core
Bus Number (BUSN):
19:15 RO 00001b Core
RESERVED ()
14:12 RO 000b Core
Function Number (FUNN):
11:0 RO 000h Core
Reserved ():
1.9
PCI Device 2 Function 0
Register
Name
Register
Symbol
Register
Start
Register
End
Default
Value
Access
Vendor
Identification
Identification
VID2 0
1
8086h
RO;
Device
Identification
Identification
DID 2
3
A001h
RO;
PCI Command
PCICMD2
4
5
0000h
RO; RW;
PCI Status
PCISTS2
6
7
0090h
RO;
Revision
Identification
Identification
RID2 8
8
02h
RO;