Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
112
Datasheet
1.9.12
GMADR - Graphics Memory Range Address
B/D/F/Type: 0/2/0/PCI
Address Offset:
18-1Bh
Default Value:
00000008h
Access:
RO; RW; RW/L;
Size: 32
bits
IGD graphics memory base address is specified in this register.
Bit Access Default
Value
Description
31:29 RW 000b
Memory Base Address (MBA):
Set by the OS, these bits correspond to
address signals [31:29].
Set by the OS, these bits correspond to
address signals [31:29].
28 RW/L 0b
512MB Address Mask (512ADMSK):
This Bit is either part of the Memory Base
Address (R/W) or part of the Address Mask
(RO), depending on the value of MSAC[1:0].
See MSAC (Dev2, Func 0, offset 62h) for
details.
This Bit is either part of the Memory Base
Address (R/W) or part of the Address Mask
(RO), depending on the value of MSAC[1:0].
See MSAC (Dev2, Func 0, offset 62h) for
details.
27 RW/L 0b
256 MB Address Mask (256ADMSK):
This bit is either part of the Memory Base
Address (R/W) or part of the Address Mask
(RO), depending on the value of MSAC[1:0].
See MSAC (Dev 2, Func 0, offset 62h) for
details.
This bit is either part of the Memory Base
Address (R/W) or part of the Address Mask
(RO), depending on the value of MSAC[1:0].
See MSAC (Dev 2, Func 0, offset 62h) for
details.
26:4 RO 000000h
Address Mask (ADM):
Hardwired to 0s to indicate at least 128MB
address range.
Hardwired to 0s to indicate at least 128MB
address range.
3 RO 1b
Prefetchable Memory (PREFMEM):
Hardwired to 1 to enable prefetching.
Hardwired to 1 to enable prefetching.
2:1 RO 00b
Memory Type (MEMTYP):
Hardwired to 0 to indicate 32-bit address.
Hardwired to 0 to indicate 32-bit address.
0 RO 0b
Memory/IO Space (MIOS):
Hardwired to 0 to indicate memory space.
Hardwired to 0 to indicate memory space.