Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
113
1.9.13
GTTADR - Graphics Translation Table Range Address
B/D/F/Type: 0/2/0/PCI
Address Offset:
1C-1Fh
Default Value:
00000000h
Access:
RO; RW;
Size: 32
bits
This register requests allocation for Graphics Translation Table Range. The allocation
is for 1 MB and the base address is defined by bits [31:20].
is for 1 MB and the base address is defined by bits [31:20].
Bit Access
Default
Value
Description
31:20 RW
000h
Memory Base Address (MBA):
Set by the OS, these bits correspond to address
signals [31:20].
Set by the OS, these bits correspond to address
signals [31:20].
19:4 RO
0000h
Address Mask (ADMSK):
Hardwired to 0s to indicate a 1 MB address range.
3 RO
0b
Prefetchable Memory (PREFMEM):
Hardwired to 0 to prevent prefetching.
Hardwired to 0 to prevent prefetching.
2:1 RO
00b
Memory Type (MEMTYP):
Hardwired to 0s to indicate 32-bit address.
Hardwired to 0s to indicate 32-bit address.
0 RO
0b
Memory/IO Space (MIOS):
Hardwired to 0 to indicate memory space.
Hardwired to 0 to indicate memory space.
1.9.14
SVID2 - Subsystem Vendor Identification
B/D/F/Type: 0/2/0/PCI
Address Offset:
2C-2Dh
Default Value:
0000h
Access:
RWO;
Size: 16
bits
Bit Access
Default
Value
Description
15:0 RWO
0000h
Subsystem Vendor ID (SUBVID):
This value is used to identify the vendor of the
subsystem. This register should be programmed by
BIOS during boot-up. Once written, this register
becomes Read_Only. This register can only be
cleared by a Reset.
This value is used to identify the vendor of the
subsystem. This register should be programmed by
BIOS during boot-up. Once written, this register
becomes Read_Only. This register can only be
cleared by a Reset.