Intel D425 AU80610006252AA User Manual

Datasheet 

 111 

31:19 RW  0000h 

Memory Base Address (MBA):  
Set by the OS, these bits correspond to address 
signals [31:19].

 

18:4 RO  0000h 

Address Mask (ADM):  
Hardwired to 0s to indicate 512 KB address 
range.

 

3 RO  0b 

Prefetchable Memory (PREFMEM):  
Hardwired to 0 to prevent prefetching. 

2:1 RO  00b 

Memory Type (MEMTYP):  
 Hardwired to 0s to indicate 32-bit address. 

0 RO  0b 

Memory / IO Space (MIOS):  
  Hardwired to 0 to indicate memory space. 

B/D/F/Type: 0/2/0/PCI 

Address Offset: 

14-17h 

Default Value: 

00000001h 

Access: 

 RO; RW; 

Size: 32 

bits 

This register provides the Base offset of the I/O registers within Device #2. Bits 15:3 
are programmable allowing the I/O Base to be located anywhere in 16bit I/O Address 

Space. Bits 2:1 are fixed and return zero, bit 0 is hardwired to a one indicating that 8 

bytes of I/O space are decoded. Access to the 8Bs of IO space is allowed in PM state 
D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1-D3 or if 

IO Enable is clear or if Device #2 is turned off or if Internal graphics is disabled. 

Note that access to this IO BAR is independent of VGA functionality within Device #2. 
Also note that this mechanism is available only through function 0 of Device#2 and is 

not duplicated in function #1. 

If accesses to this IO bar is allowed then the CPU Uncore claims all 8, 16 or 32 bit IO 
cycles from the CPU that falls within the 8B claimed. 

31:16 RO  0000h 

Reserved ():  
Read as "0", these bits correspond to address 
signals [31:16].

 

15:3 RW  0000h 

IO Base Address (IOBASE):  
Set by the OS, these bits correspond to 
address signals [15:3].

 

2:1 RO  00b 

Memory Type (MEMTYPE):  
Hardwired to 0s to indicate 32-bit address.

 

0 RO  1b 

Memory/IO Space (MIOS):  
Hardwired to "1" to indicate IO space.