Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
126
Datasheet
1.9.34
GDRST - Graphics Debug Reset
B/D/F/Type: 0/2/0/PCI
Address Offset:
C0h
Default Value:
00h
Access:
RO; RW;
Size: 8
bits
Bit Access Default
Value
Description
7:4 RO 0h
Reserved ():
3:2 RW 00b
Graphics Reset Domain (GRDOM):
Graphics Reset Domain
00 – Full Graphics Reset will be performed
(both render and display clock domain resets
asserted
01 – Reserved (Illegal Programming)
10 – Reserved (Illegal Programming)
11 – Reserved (Illegal Programming)
Graphics Reset Domain
00 – Full Graphics Reset will be performed
(both render and display clock domain resets
asserted
01 – Reserved (Illegal Programming)
10 – Reserved (Illegal Programming)
11 – Reserved (Illegal Programming)
1 RO 0b
Reserved ():
0 RW 0b
Graphics Reset Enable (GR):
Setting this bit asserts graphics-only reset. The
clock domains to be reset are determined by
GRDOM. Hardware resets this bit when the
reset is complete. Setting this bit without
waiting for it to clear, is undefined behavior.
Once this bit is set to a "1" all GFX core MMIO
registers are returned to power on default
state. All Ring buffer pointers are reset,
command stream fetches are dropped and
ongoing render pipeline processing is halted,
state machines and State Variables returned to
power on default state. If the Display is reset,
all display engines are halted (garbage on
screen). VGA memory is not available, Store
DWORDs and interrupts are not guaranteed to
be completed. Device #2 IO registers are not
available.
Device #2 Config registers continue to be
available while Graphics reset is asserted.
This bit is HW auto-clear.
Setting this bit asserts graphics-only reset. The
clock domains to be reset are determined by
GRDOM. Hardware resets this bit when the
reset is complete. Setting this bit without
waiting for it to clear, is undefined behavior.
Once this bit is set to a "1" all GFX core MMIO
registers are returned to power on default
state. All Ring buffer pointers are reset,
command stream fetches are dropped and
ongoing render pipeline processing is halted,
state machines and State Variables returned to
power on default state. If the Display is reset,
all display engines are halted (garbage on
screen). VGA memory is not available, Store
DWORDs and interrupts are not guaranteed to
be completed. Device #2 IO registers are not
available.
Device #2 Config registers continue to be
available while Graphics reset is asserted.
This bit is HW auto-clear.