Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
125
Bit Access Default
Value
Description
0 RW 0b
MSI Enable (MSIEN):
Controls the ability of this device to generate
MSIs.
Controls the ability of this device to generate
MSIs.
1.9.32
MA - Message Address
B/D/F/Type: 0/2/0/PCI
Address Offset:
Address Offset:
94-97h
Default Value:
00000000h
Access:
RW; RO;
Size: 32
bits
Bit Access Default
Value
Description
31:2 RW
00000000
h
Message Address (MESSADD):
Used by system software to assign an MSI
address to the device.
The device handles an MSI by writing the
padded contents of the MD register to this
address.
Used by system software to assign an MSI
address to the device.
The device handles an MSI by writing the
padded contents of the MD register to this
address.
1:0 RO 00b
Force Dword Align (FDWORD):
Hardwired to 0 so that addresses assigned by
system software are always aligned on a
DWORD address boundary.
Hardwired to 0 so that addresses assigned by
system software are always aligned on a
DWORD address boundary.
1.9.33
MD - Message Data
B/D/F/Type: 0/2/0/PCI
Address Offset:
98-99h
Default Value:
0000h
Access:
RW;
Size: 16
bits
Bit Access Default
Value
Description
15:0 RW 0000h
Message Data (MESSDATA):
Base message data pattern assigned by system
software and used to handle an MSI from the
device.
When the device must generate an interrupt
request, it writes a 32-bit value to the memory
address specified in the MA register. The upper
16 bits are always set to 0. The lower 16 bits
are supplied by this register.
Base message data pattern assigned by system
software and used to handle an MSI from the
device.
When the device must generate an interrupt
request, it writes a 32-bit value to the memory
address specified in the MA register. The upper
16 bits are always set to 0. The lower 16 bits
are supplied by this register.