Intel D425 AU80610006252AA User Manual

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Datasheet  

B/D/F/Type: 0/2/0/PCI 

Address Offset: 

92-93h 

Default Value: 

0000h 

Access: 

 RO; RW; 

Size: 16 

bits 

System software can modify bits in this register, but the device is prohibited from 
doing so.  If the device writes the same message multiple times, only one of those 

messages is guaranteed to be serviced.  If all of them must be serviced, the device 
must not generate the same message again until the driver services the earlier one. 

 

 

15:8 RO  00h 

7 RO  0b 

64 Bit Capable (64BCAP):  
 Hardwired to 0 to indicate that the function 
does not implement the upper 32 bits of the 
Message address register and is incapable of 
generating a 64-bit memory address. 
This may need to change in future 
implementations when addressable system 
memory exceeds the 32b/4GB limit.

 

6:4 RW  000b 

Multiple Message Enable (MME):  
  System software programs this field to 
indicate the actual number of messages 
allocated to this device. This number will be 
equal to or less than the number actually 
requested. 
The encoding is the same as for the MMC field 
below. 

3:1 RO  000b 

Multiple Message Capable (MMC):  
 System Software reads this field to determine 
the number of messages being requested by 
this device. 
Value:  Number of requests 
000: 1 
All of the following are reserved in this 
implementation 
001: 2 
010: 4 
011: 8 
100: 16 
101: 32 
110: Reserved 
111: Reserved