Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
36
Datasheet
1.5.7
MLT - Master Latency Timer
B/D/F/Type: 0/0/0/PCI
Address Offset:
Dh
Default Value:
00h
Access:
RO;
Size: 8
bits
Device #0 in the CPU Uncore is not a PCI master. Therefore this register is not
implemented.
implemented.
Bit Access Default
Value
RST/
PWR
Description
7:0 RO 00h Core
Reserved ():
1.5.8
HDR - Header Type
B/D/F/Type: 0/0/0/PCI
Address Offset:
Eh
Default Value:
00h
Access:
RO;
Size: 8
bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
register exists at this location.
Bit Access Default
Value
RST/
PWR
Description
7:0 RO 00h Core
PCI Header (HDR):
This field always returns 0 to indicate that the
CPU Uncore is a single function device with
standard header layout. Reads and writes to
this location have no effect.
This field always returns 0 to indicate that the
CPU Uncore is a single function device with
standard header layout. Reads and writes to
this location have no effect.
1.5.9
SVID - Subsystem Vendor Identification
B/D/F/Type: 0/0/0/PCI
Address Offset:
2C-2Dh
Default Value:
0000h
Access:
RWO;
Size: 16
bits
This value is used to identify the vendor of the subsystem.
Bit Access Default
Value
RST/
PWR
Description
15:0 RWO 0000h Core
Subsystem Vendor ID (SUBVID):
This field should be programmed during boot-
up to indicate the vendor of the system board.
After it has been written once, it becomes read
only.
This field should be programmed during boot-
up to indicate the vendor of the system board.
After it has been written once, it becomes read
only.