Intel D425 AU80610006252AA User Manual

38  

Datasheet  

63:36 RO 0000000h 

Core 

35:12 RW/L 000000h Core 

PCI Express Egress Port MMIO Base 
Address (PXPEPBAR):  
This field corresponds to bits 35 to 12 of the 
base address PCI Express Egress Port MMIO 
configuration space. BIOS will program this 
register resulting in a base address for a 4KB 
block of contiguous memory address space. This 
register ensures that a naturally aligned 4 KB 
space is allocated within the first 64 GB of 
addressable memory space. System Software 
uses this base address to program the CPU 
Uncore MMIO register set.  

11:1 RO  000h Core 

0 RW/L  0b  Core 

0:

 

PXPEPBAR is disabled and does not claim any 

memory 

1:

 

PXPEPBAR memory mapped accesses are 

claimed and decoded appropriately 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

48-4Fh 

Default Value: 

0000000000000000h 

Access: 

 RW/L; RO; 

Size: 64 

bits 

This is the base address for the CPU Uncore Memory Mapped Configuration space. 
There is no physical memory within this 16KB window that can be addressed. The 

16KB reserved by this register does not alias to any PCI 2.3 compliant memory 

mapped space. On reset, the CPU Uncore MMIO Memory Mapped Configuration space 
is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0] 

The register space contains memory control, initialization, timing, and buffer strength 

registers; clocking registers; and power and thermal management registers.  

 

 

63:36 RO 0000000h 

Core 

35:14 RW/L 000000h Core 

GMCH Memory Mapped Base Address 
(MCHBAR):  
 This field corresponds to bits 35 to 14 of the 
base address GMCH Memory Mapped 
configuration space. BIOS will program this 
register resulting in a base address for a 16KB 
block of contiguous memory address space. 
This register ensures that a naturally aligned 
16KB space is allocated. System Software 
uses this base address to program the GMCH 
Memory Mapped register set.