Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
37
1.5.10
SID - Subsystem Identification
B/D/F/Type: 0/0/0/PCI
Address Offset:
2E-2Fh
Default Value:
0000h
Access:
RWO;
Size: 16
bits
This value is used to identify a particular subsystem.
Bit Access Default
Value
RST/
PWR
Description
15:0 RWO 0000h Core
Subsystem ID (SUBID):
This field should be programmed during BIOS
initialization. After it has been written once, it
becomes read only.
This field should be programmed during BIOS
initialization. After it has been written once, it
becomes read only.
1.5.11
CAPPTR - Capabilities Pointer
B/D/F/Type: 0/0/0/PCI
Address Offset:
34h
Default Value:
E0h
Access:
RO;
Size: 8
bits
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
capability in the capability list.
Bit Access Default
Value
RST/
PWR
Description
7:0 RO E0h Core
Capabilities Pointer (CAPPTR):
Pointer to the offset of the first capability ID
register block. In this case the first capability
is the product-specific Capability Identifier
(CAPID0).
Pointer to the offset of the first capability ID
register block. In this case the first capability
is the product-specific Capability Identifier
(CAPID0).
1.5.12
PXPEPBAR - PCI Express Egress Port Base Address
B/D/F/Type: 0/0/0/PCI
Address Offset:
Address Offset:
40-47h
Default Value:
0000000000000000h
Access:
RW/L; RO;
Size: 64
bits
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4KB window that can be addressed. The 4KB
There is no physical memory within this 4KB window that can be addressed. The 4KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].