Intel D425 AU80610006252AA User Manual

Product codes
AU80610006252AA
Page of 153
 
Processor Configuration Registers 
 
 
 
Datasheet 
 51 
1.5.24 
PAM6 - Programmable Attribute Map 6 
B/D/F/Type: 0/0/0/PCI 
Address Offset: 
96h 
Default Value: 
00h 
Access: 
 RO; RW/L; 
Size: 8 
bits 
This register controls the read, write, and shadowing attributes of the BIOS areas 
from 0E8000h- 0EFFFFh. 
 
 
Bit Access Default 
Value 
RST/
PWR 
Description 
7:6 RO  00b Core 
Reserved () 
5:4 RW/L  00b  Core 
0EC000-0EFFFF Attribute (HIENABLE):  
 This field controls the steering of read and 
write cycles that address the BIOS area from 
0E4000 to 0E7FFF. 
00:  DRAM Disabled: Accesses are directed to 
DMI. 
01:  Read Only: All reads are serviced by 
DRAM. All writes are forwarded to DMI. 
10:  Write Only: All writes are sent to DRAM. 
Reads are serviced by DMI. 
11:  Normal DRAM Operation: All reads and 
writes are serviced by DRAM. 
3:2 RO  00b Core 
Reserved ():  
1:0 RW/L  00b  Core 
0E8000-0EBFFF Attribute (LOENABLE):  
 This field controls the steering of read and 
write cycles that address the BIOS area from 
0E0000 to 0E3FFF. 
00:  DRAM Disabled: Accesses are directed to 
DMI. 
01:  Read Only: All reads are serviced by 
DRAM. All writes are forwarded to DMI. 
10:  Write Only: All writes are sent to DRAM. 
Reads are serviced by DMI. 
11:  Normal DRAM Operation: All reads and 
writes are serviced by DRAM.