Intel D425 AU80610006252AA User Manual

Datasheet 

 53 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

9A-9Bh 

Default Value: 

0000h 

Access: 

 RO; RW/L; 

Size: 16 

bits 

 

15:10 RO 000000b 

Core 

9:0 RW/L  000h Core 

Remap Limit Address [35:26] (REMAPLMT):  
 The value in this register defines the upper 
boundary of the Remap window. The Remap 
window is inclusive of this address.  In the 
decoder A[25:0] of the remap limit address are 
assumed to be F's. Thus the top of the defined 
range will be one less than a 64MB boundary. 

When the value in this register is less than the 
value programmed into the Remap Base 
register, the Remap window is disabled. 

B/D/F/Type: 0/0/0/PCI 
Address Offset: 

9Dh 

Default Value: 

02h 

Access: 

 RO; RW/L; RW; RW/L/K; 

Size: 8 

bits 

The SMRAMC register controls how accesses to Compatible and Extended SMRAM 
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit 

is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set. 

 

 

7 RO  0b Core 

6 RW/L  0b  Core 

SMM Space Open (D_OPEN):  
 When D_OPEN=1 and D_LCK=0, the SMM 
space DRAM is made visible even when SMM 
decode is not active. This is intended to help 
BIOS initialize SMM space. Software should 
ensure that D_OPEN=1 and D_CLS=1 are not 
set at the same time. 

5 RW  0b Core 

SMM Space Closed (D_CLS):  
 When D_CLS = 1 SMM space DRAM is not 
accessible to data references, even if SMM 
decode is active. Code references may still 
access SMM space DRAM. This will allow SMM 
software to reference through SMM space to