Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
52
Datasheet
1.5.25
LAC - Legacy Access Control
B/D/F/Type: 0/0/0/PCI
Address Offset:
97h
Default Value:
00h
Access:
RW/L; RO;
Size: 8
bits
This 8-bit register controls a fixed DRAM hole from 15-16 MB.
Bit Access Default
Value
RST/
PWR
Description
7 RW/L 0b Core
Hole Enable (HEN):
This field enables a memory hole in DRAM
space. The DRAM that lies "behind" this space is
not remapped.
0: No memory hole.
1: Memory hole from 15 MB to 16 MB.
This field enables a memory hole in DRAM
space. The DRAM that lies "behind" this space is
not remapped.
0: No memory hole.
1: Memory hole from 15 MB to 16 MB.
6:0 RO 00h Core
Reserved ():
1.5.26
REMAPBASE - Remap Base Address Register
B/D/F/Type: 0/0/0/PCI
Address Offset:
98-99h
Default Value:
03FFh
Access:
RO; RW/L;
Size: 16
bits
Bit Access Default
Value
RST/
PWR
Description
15:10 RO 000000b
Core
Reserved ()
9:0 RW/L 3FFh Core
Remap Base Address [35:26]
(REMAPBASE):
The value in this register defines the lower
boundary of the Remap window. The Remap
window is inclusive of this address. In the
decoder A[25:0] of the Remap Base Address are
assumed to be 0's. Thus the bottom of the
defined memory range will be aligned to a 64MB
boundary.
(REMAPBASE):
The value in this register defines the lower
boundary of the Remap window. The Remap
window is inclusive of this address. In the
decoder A[25:0] of the Remap Base Address are
assumed to be 0's. Thus the bottom of the
defined memory range will be aligned to a 64MB
boundary.
When the value in this register is greater than
the value programmed into the Remap Limit
register, the Remap window is disabled.
the value programmed into the Remap Limit
register, the Remap window is disabled.