Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
66
Datasheet
Bit Access Default
Value
RST/
PWR
Description
7:0 RO 09h Core
Capability Identifier (CAP_ID):
This field has the value 1001b to identify the
CAP_ID assigned by the PCI SIG for vendor
dependent capability pointers.
This field has the value 1001b to identify the
CAP_ID assigned by the PCI SIG for vendor
dependent capability pointers.
1.6
MCHBAR
Register Name
Register
Symbol
Register
Start
Register End
Default
Value
Access
Channel Decode
Misc
Misc
CHDECMISC 111
111
00h
RW/L;
RO;
Channel 0 DRAM
Rank Boundary
Address 0
Rank Boundary
Address 0
C0DRB0 200
201
0000h RW/L;
RO;
Channel 0 DRAM
Rank Boundary
Address 1
Rank Boundary
Address 1
C0DRB1 202
203
0000h RW/L;
RO;
Channel 0 DRAM
Rank Boundary
Address 2
Rank Boundary
Address 2
C0DRB2 204
205
0000h RW/L;
RO;
Channel 0 DRAM
Rank Boundary
Address 3
Rank Boundary
Address 3
C0DRB3 206
207
0000h RW/L;
RO;
Channel 0 DRAM
Rank 0,1 Attribute
Rank 0,1 Attribute
C0DRA01 208
209
0000h
RW/L;
Channel 0 DRAM
Rank 2,3 Attribute
Rank 2,3 Attribute
C0DRA23 20A
20B
0000h
RW/L;
Channel 0 CYCTRK
PCHG
PCHG
C0CYCTRKP
CHG
250 251 0000h
RO;
RW;
Channel 0 CYCTRK
ACT
ACT
C0CYCTRKA
CT
252 255
00000000h
RW;
RO;
Channel 0 CYCTRK
WR
WR
C0CYCTRKW
R
256 257 0000h RW;
Channel 0 CYCTRK
READ
READ
C0CYCTRKR
D
258 25A 000000h
RW;
RO;
Channel 0 CYCTRK
REFR
REFR
C0CYCTRKR
EFR
25B 25C 0000h
RO;
RW;
Channel 0 CKE
Control
Control
C0CKECTRL 260
263
00000800h
RW; RW/L;
RO;
Channel 0 DRAM
Refresh Control
Refresh Control
C0REFRCTR
L
269 26E
241830000C30
h
RW; RO;
Channel 0 ODT
Control
Control
C0ODTCTRL 29C
29F
00000000h RO;
RW;