Intel D425 AU80610006252AA User Manual

Datasheet 

 67 

Power Management 
Status 

PMSTS F14 

F17  00000000h 

RWC/P; 

RO; 

B/D/F/Type: 0/0/0/MCHBAR 
Address Offset: 

111h 

Default Value: 

00h 

Access: 

 RW/L; RO; 

Size: 8 

bits 

Misc. CHDEC/MAGEN configuration bits 

 

 

7 RW/L  0b  Core 

Enhanced Address for DIMM Select 
(ENHDIMMSEL):  
This bit can be set when enhanced mode of 
addressing for ranks are enabled and all four 
ranks are populated with equal amount of 
memory. This should be disabled  when EP is 
present. 
0 = Use Standard methods for DIMM Select. 
1 = Use Enhanced Address as DIMM Select. 

6:5 RW/L  00b  Core 

Enhanced Mode Select (ENHMODESEL):  
00 = Swap Enabled for Bank Selects and 
Rank Selects 
01 = XOR Enabled for Bank Selects and Rank 
Selects 
10 = Swap Enabled for Bank Selects only 
11 = XOR Enabled for Bank Select only 

4:3 RO  00b Core 

2 RW/L  0b  Core 

Ch0 Enhanced Mode (CH0_ENHMODE):  
This bit indicates that enhanced addressing 
mode of operation is enabled for ch0 
Enhanced addressing mode of operation 
should be enabled only when both the 
channels are equally populated with same 
size and same type of DRAM memory. 
An added restriction is that the number of 
ranks/channel has to be 1, 2 or 4. 

NOTE:  If any of the two channels is in 

enhanced mode, the other channel 
should also be in enhanced mode.  

1:0 RO  00b Core