Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
68
Datasheet
1.6.2
C0DRB0 - Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
200-201h
Default Value:
0000h
Access:
RW/L; RO;
Size: 16
bits
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64MB. Each rank has its own single-word DRB register.
rank with a granularity of 64MB. Each rank has its own single-word DRB register.
These registers are used to determine which chip select will be active for a given
address. Channel and rank map:
address. Channel and rank map:
ch0 rank0: 200h
ch0 rank1: 202h
ch0 rank2: 204h
ch0 rank3: 206h
ch0 rank1: 202h
ch0 rank2: 204h
ch0 rank3: 206h
Programming guide:
1. Non-stacked mode:
1. Non-stacked mode:
If Channel 0 is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in ch0 rank0 (in 64MB increments)
C0DRB1 = Total memory in ch0 rank0 + ch0 rank1 (in 64MB increments)
and so on.
C0DRB0 = Total memory in ch0 rank0 (in 64MB increments)
C0DRB1 = Total memory in ch0 rank0 + ch0 rank1 (in 64MB increments)
and so on.
2. Stacked mode:
CODRBs:
Similar to Non-stacked mode.
Similar to Non-stacked mode.
Bit Access Default
Value
RST/
PWR
Description
15:10 RO 000000b
Core
Reserved ():
9:0 RW/L 000h Core
Channel 0 Dram Rank Boundary Address 0
(C0DRBA0):
This register defines the DRAM rank boundary
for rank0 of Channel 0 (64 MB granularity)
=R0
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
(C0DRBA0):
This register defines the DRAM rank boundary
for rank0 of Channel 0 (64 MB granularity)
=R0
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB