Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
72
Datasheet
1.6.7
C0DRA23 - Channel 0 DRAM Rank 2, 3 Attribute
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
20A-20Bh
Default Value:
0000h
Access:
RW/L;
Size: 16
bits
See C0DRA01
Bit Access Default
Value
RST/
PWR
Description
15:8 RW/L 00h Core
Channel 0 DRAM Rank-3 Attributes
(C0DRA3):
This register defines DRAM page size/number-
of-banks for rank3 for given channel
(C0DRA3):
This register defines DRAM page size/number-
of-banks for rank3 for given channel
See table in register description for
programming
programming
7:0 RW/L 00h Core
Channel 0 DRAM Rank-2 Attributes
(C0DRA2):
This register defines DRAM page size/number-
of-banks for rank2 for given channel
(C0DRA2):
This register defines DRAM page size/number-
of-banks for rank2 for given channel
See table in register description for
programming
programming
1.6.8
C0CYCTRKPCHG - Channel 0 CYCTRK PCHG
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
250-251h
Default Value:
0000h
Access:
RO; RW;
Size: 16
bits
Channel 0 CYCTRK Precharge Registers.
Bit Access Default
Value
RST
/PWR
Description
15:11 RO 00000b Core
Reserved ():
Reserved.
Reserved.
10:6 RW 00000b
Core
Write To PRE Delayed (C0sd_cr_wr_pchg):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between the WRITE and PRE commands to the
same rank-bank. Corresponds to tWR at DDR
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between the WRITE and PRE commands to the
same rank-bank. Corresponds to tWR at DDR
Specification.
5:2 RW 0000b
Core
READ To PRE Delayed (C0sd_cr_rd_pchg):
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between the READ and PRE commands to the
same rank-bank.
This configuration register indicates the
minimum allowed spacing (in DRAM clocks)
between the READ and PRE commands to the
same rank-bank.