Intel D425 AU80610006252AA User Manual

Datasheet 

 73 

1:0 RW  00b Core 

PRE To PRE Delayed (C0sd_cr_pchg_pchg):  
This configuration register indicates the 
minimum allowed spacing (in DRAM clocks) 
between two PRE commands to the same rank. 

B/D/F/Type: 0/0/0/MCHBAR 

Address Offset: 

252-255h 

Default Value: 

00000000h 

Access: 

 RW; RO; 

Size: 32 

bits 

Channel 0 CYCTRK Activate Registers. 

 

 

31:28 RO 

0h  Core 

27:22 RW 000000b 

Core 

ACT Window Count 
(C0sd_cr_act_windowcnt):  
This configuration register indicates the window 
duration (in DRAM clocks) during which the 
controller counts the # of activate commands 
which are launched to a particular rank. If the 
number of activate commands launched within 
this window is greater than 4, then a check is 
implemented to block launch of further 
activates to this rank for the rest of the 
duration of this window.          

21 RW  0b Core 

Max ACT Check Disable 
(C0sd_cr_maxact_dischk):  
This configuration register disenables the 
check, which ensures that there are no more 
than four activates to a particular rank in a 
given window. 

20:17 RW  0000b Core 

ACT to ACT Delayed (C0sd_cr_act_act[):  
This configuration register indicates the 
minimum allowed spacing (in DRAM clocks) 
between two ACT commands to the same rank. 
Corresponds to tRRD at DDR Spec. 

16:13 RW  0000b Core 

PRE to ACT Delayed (C0sd_cr_pre_act):  
This configuration register indicates the 
minimum allowed spacing (in DRAM clocks) 
between the PRE and ACT commands to the 
same rank-bank:12:9R/W0000bPRE-ALL to 
ACT Delayed (C0sd_cr_preall_act):This 
configuration register indicates the minimum 
allowed spacing (in DRAM clocks) between the 
PRE-ALL and ACT commands to the same 
rank.  Corresponds to tRP at DDR Spec.